The present invention relates to a technical idea capable of being effectively applied to a tightly-coupled multiprocessor system which shares a main memory, and a coherency control technique of data of the tightly-coupled multiprocessor system.
In a tightly-coupled multiprocessor system in which a plurality of processors each having cache memories share a main memory, data at the same address on the main memory are present in the cache memories of the plural processors in a distributed manner. At this time, in such a multiprocessor system that when data of other main memory addresses allocated to the same cache line are read, updated data are written back to the main memory, the data distributed to the cache memories on the plural processors are individually updated, and therefore, there are some possibilities that these individually updated data are different from the address of the same addresses on the main memory. As a consequence, in the case that a data reading access is issued from an arbitrary processor to the main memory, it is necessarily require to assure time sequential coherency as to the data stored in the cache memories on the respective processors and the data stored in the main memory.
Conventionally, as coherency control methods of data in such a tightly-coupled multiprocessor system in which a plurality of processors each having cache memories share a main memory, the technical ideas are known and described in, for instance, M. S. Papamarcos and J. H. Patel, “A Low-overhead Coherence Solution for Multiprocessors with Private Cache Memories,” Proc. the 11th International Symposium on Computer Architecture, 1984, pp. 284-290. In the conventional coherency control methods, cache states of data are managed by the following 4 items: (1) Invalid (data of subject cache memory is invalid); (2) Shared-Unmodified (same data as that of main memory is also present in cache memory provided in another processor); (3) Exclusive-Unmodified (same data as that of main memory is present only in subject cache memory); and (4) Exclusive-Modified (updated data is present only in subject cache memory). A data reading access issued from a processor is broadcasted to all of nodes in order that a judgement is made as to whether the latest data is present in a cache memory, or the main memory by confirming data cache states of the cache memories on the processors provided in all of the nodes which constructs the tightly-coupled multiprocessor system. Also, when data of a cache line is updated, in such a case that data of another main memory address allocated to the same cache line is read, a data write-back access is issued from the processor and thus the updated data is transferred to the main memory.
At this time, the conventional technique owns such a problem that a contradiction occurs in coherency of data, since a data reading access issued from a processor of a node and a data write-back access issued from another node passes each other on the tightly-coupled multiprocessor system.
As one solution of the above-problem, there is such a method capable of preventing an occurrence of passing each other. That is, a confirmation is made as to whether or not the data reading access directed to the same address has been issued before the data write-back access is issued on the tightly-coupled multiprocessor system, and when such an access has been issued, the write-back data is transmitted to the processor which issues the data reading access, and the data is written back to the main memory. However, this first solution owns another technical problem that the system performance is deteriorated. As a second solution of the above-explained problem, U.S. Pat. No. 6,298,418B1 has proposed such a tightly-coupled multiprocessor system equipped with a means for notifying a completion of an issued data write-back access to a main memory. Since the means for notifying the completion of the data write-back access is employed, the node which issued the data write-back access can correctly recognize the timing at which the updating operation of the main memory data is assured. In the second solution, the occurrence of the deviation between the data reading access and the data write-back access is allowed between the nodes, and it is possible to avoid the deterioration of the system performance.
In the above-described second solution, since the orders of the data reading accesses and the data write-back accesses which are transferred to the same node are not replaced with each other, the data reading access and the data write-back access cannot be carried out in accordance with processing conditions in the respective nodes. At this time, the data reading access to the main memory normally requires lengthy time. If the above-explained item is solved and the data reading access to the main memory can be carried out in an advance manner, then the system performance may be greatly improved.